Avago’s 25-Gbps Serialiser/Deserialiser (SerDes) core in 28-nm process technology has demonstrated compliance with the Common Electrical Interface (CEI) standard for 25G Long Reach (LR). Achieving CEI-25G-LR compliance eases design of data networking applications and aligns with the push for 100G Ethernet Infrastructure to extend cloud computing, multimedia and virtualisation capabilities.The company demonstrated its 25G SerDes cores in backplane applications at DesignCon 2012 in Santa Clara. The embedded SerDes cores are often integrated in ASICs used for data communication in networking, computing and storage applications. The demonstrations showed the Avago 25G SerDes running on over 30-inch PC board traces.
Avago Intellectual Property (IP) SerDes cores can be easily integrated due to their modular, multirate architecture, and Avago has integrated over 400 SerDes channels on a single ASIC. The 28-nm Avago SerDes cores feature a unique decision feedback equalisation (DFE) architecture, resulting in a number of key performance differentiators such as low overall power, best-in-class data latency, and best-in-class jitter and crosstalk tolerance.
“This compliance is not only another first for our SerDes cores, but it marks a significant step forward in the march to 100G Ethernet Infrastructure,” said Frank Ostojic, vice president and general manager of the ASIC Products Division at Avago. “As part of the push toward 100G, Avago is planning to use our 25G SerDes as the basis for future standard products. Capable of driving 5 meters of copper cabling at low power, the 25G SerDes is suitable for a range of applications and is now available to a larger group of customers.”
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