Mobile World Congress: TI collaborates with Aricent on small cell protocol stack

TI and Aricent announced at Mobile World Congress that they have collaborated on a small cell protocol stack optimised for TI’s KeyStone-based multicore SoCs. According to the companies, integrating TI’s KeyStone architecture element for Layers 2, 3 and transport processing with Aricent’s software components enables more cost-efficient and high performance base stations.

TI’s scalable KeyStone architecture includes support for both TMS320C66x digital signal processor generation cores and multiple cache coherent quad ARM Cortex-A15 clusters, for a mixture of up to 32 DSP and RISC cores.  In addition, TI’s KeyStone architecture includes fully offloaded, flexible packet and security coprocessors and capacity expansion for SoC structural elements such as TeraNet, Multicore  Navigator and Multicore Shared Memory Controller (MSMC). These structural elements provide a seamless integration between the DSP and ARM RISC cores, allowing base station developers to fully utilise the capability of all processing elements, including the cores and enhanced AccelerationPacs.

“The combination of TI’s industry-leading KeyStone multicore DSPs and Aricent’s proven software frameworks creates powerful , reliable and cost-efficient base station solutions for operators,” said Rakesh Vij, vice president of business development, Aricent Group. “Our small cell protocol stack has been chosen by several leading OEM vendors and is in advanced trials or production systems today. This collaboration further cements our leadership in providing world-class LTE software. Our software together with our product engineering services help OEMs to introduce innovative new solutions to the market quickly and efficiently.”

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